BISS encoder module. Unidirectional BISS interface, 512 bits maximum

BISS Data register
0x4A00 BISS 0 32 bit data register
0x4A04 BISS 1 32 bit data register
0x4A08 BISS 2 32 bit data register
...

This register is the top of a 16 deep x32 wide LIFO stack.
BISS data sizes greater that 32 bits are read by muliple reads
of the same address. Data is returned LSW first and right justified.
Writes to the data register start a data transfer in selected channel

BISS Control register 0
0x4B00 BISS 0 Control register
0x4B04 BISS 0 Control register
0x4B08 BISS 0 Control register
...

Bits 31..16     BISS DDS data rate register
Bits 15..10     BISS data digital filter setting in units of ClockHigh
Bits  9..0      BISS data bits (1 to 512)

The BISS data rate field sets the BISS clock rate. This rate is
(ClockHigh/65536)*BISS_DataRateReg

BISS Control register 1
0x4C00
0x4C04
0x4C08
...

Bit 15          SyncDAV status (read only)
Bits 14..12     DPLL Timer select register
Bit 10          RGo status (read only)
Bit  9          TStartMask
Bit  8          PStartMask
Bits 4..0       words of Data to read (Read Only)

The timer select register selects the desired timer output
from the DPLL timer module: 0=Ref 1=timer1, 2=timer2, 3=timer3, 4=timer4
The TStartMask must be set to enable timer starts. The PStartMask
must be set to enable global starts.

BISS Global start register/busy status register
0x4D00      Writes to the global start register start data transfers in all
            BISS module that have the PStartMask set
            Reads here read back the busy status of each BISS module
            bit 0 high = module 0 busy, bit 1 high = module 1 busy etc