Configuration Name: HOSTMOT2 General configuration information: BoardName : MESA7I43 FPGA Size: 400 KGates FPGA Pins: 144 Number of IO Ports: 2 Width of one I/O port: 24 Clock Low frequency: 50.0000 MHz Clock High frequency: 100.0000 MHz Modules in configuration: Module: WatchDog There are 1 of WatchDog in configuration Version: 0 Registers: 3 BaseAddress: 0C00 ClockFrequency: 50.000 MHz Module: IOPort There are 2 of IOPort in configuration Version: 0 Registers: 5 BaseAddress: 1000 ClockFrequency: 50.000 MHz Module: MuxQCnt There are 6 of MuxQCnt in configuration Version: 3 Registers: 5 BaseAddress: 3500 ClockFrequency: 50.000 MHz Module: MuxQSel There are 1 of MuxQSel in configuration Version: 0 Registers: 0 BaseAddress: 0000 ClockFrequency: 50.000 MHz Module: StepGen There are 6 of StepGen in configuration Version: 2 Registers: 10 BaseAddress: 2000 ClockFrequency: 50.000 MHz Module: PWM There are 6 of PWM in configuration Version: 0 Registers: 5 BaseAddress: 4000 ClockFrequency: 100.000 MHz Module: LED There are 1 of LED in configuration Version: 0 Registers: 1 BaseAddress: 0200 ClockFrequency: 50.000 MHz Configuration pin-out: IO Connections for P4 Pin# I/O Pri. func Sec. func Chan Pin func Pin Dir 1 0 IOPort PWM 0 /Enable (Out) 3 1 IOPort MuxQCnt 0 MuxQ-A (In) 5 2 IOPort MuxQCnt 0 MuxQ-B (In) 7 3 IOPort MuxQCnt 0 MuxQ-IDX (In) 9 4 IOPort MuxQCnt 1 MuxQ-A (In) 11 5 IOPort MuxQCnt 1 MuxQ-B (In) 13 6 IOPort MuxQCnt 1 MuxQ-IDX (In) 15 7 IOPort MuxQCnt 2 MuxQ-A (In) 17 8 IOPort MuxQCnt 2 MuxQ-B (In) 19 9 IOPort MuxQCnt 2 MuxQ-IDX (In) 21 10 IOPort MuxQSel 0 MuxSel0 (Out) 23 11 IOPort PWM 0 PWM (Out) 25 12 IOPort PWM 0 Dir (Out) 27 13 IOPort PWM 1 PWM (Out) 29 14 IOPort PWM 1 Dir (Out) 31 15 IOPort PWM 2 PWM (Out) 33 16 IOPort PWM 2 Dir (Out) 35 17 IOPort PWM 3 PWM (Out) 37 18 IOPort PWM 3 Dir (Out) 39 19 IOPort PWM 4 PWM (Out) 41 20 IOPort PWM 4 Dir (Out) 43 21 IOPort PWM 5 PWM (Out) 45 22 IOPort PWM 5 Dir (Out) 47 23 IOPort PWM 0 /Enable (Out) IO Connections for P3 Pin# I/O Pri. func Sec. func Chan Pin func Pin Dir 1 24 IOPort StepGen 0 Step/Table1 (Out) 3 25 IOPort StepGen 0 Dir/Table2 (Out) 5 26 IOPort StepGen 1 Step/Table1 (Out) 7 27 IOPort StepGen 1 Dir/Table2 (Out) 9 28 IOPort StepGen 2 Step/Table1 (Out) 11 29 IOPort StepGen 2 Dir/Table2 (Out) 13 30 IOPort StepGen 3 Step/Table1 (Out) 15 31 IOPort StepGen 3 Dir/Table2 (Out) 17 32 IOPort StepGen 4 Step/Table1 (Out) 19 33 IOPort StepGen 4 Dir/Table2 (Out) 21 34 IOPort StepGen 5 Step/Table1 (Out) 23 35 IOPort StepGen 5 Dir/Table2 (Out) 25 36 IOPort None 27 37 IOPort None 29 38 IOPort None 31 39 IOPort None 33 40 IOPort None 35 41 IOPort None 37 42 IOPort None 39 43 IOPort None 41 44 IOPort None 43 45 IOPort None 45 46 IOPort None 47 47 IOPort None